********************************
* Copyright:                   *
* Vishay Intertechnology, Inc. *
********************************
*Apr 14, 2014
*ECN S14-0792, Rev. A
*File Name: Si7149ADP_PS.txt and Si7149ADP_PS.lib
*This document is intended as a SPICE modeling guideline and does not
*constitute a commercial product datasheet. Designers should refer to the
*appropriate datasheet of the same number for guaranteed specification
*limits.
.SUBCKT Si7149ADP D G S 
M1 3 GX S S PMOS W= 11335000u L= 0.25u 
M2 S GX S D NMOS W= 11335000u L= 0.245u 
R1 D 3 2.260e-03 TC=3.007e-03, 8.617e-06 
CGS GX S 3.235e-09 
CGD GX D 2.914e-10 
RG G GY 2.4 
RTCV 100 S 1e6 TC=0, 0
ETCV GY GX 100 200 1 
ITCV S 100 1u 
VTCV 200 S 1 
DBD D S DBD 11335000u 
**************************************************************** 
.MODEL PMOS PMOS ( LEVEL = 3 TOX = 6.5e-8 
+ RS = 0 KP = 1.856e-06 NSUB = 1.908e+16 
+ KAPPA = 4.293e-03 NFS = 1.000e+12 
+ LD = 0 IS = 0 TPG = -1 ) 
*************************************************************** 
.MODEL NMOS NMOS ( LEVEL = 3 TOX = 6.5e-8 
+NSUB = 1.737e+16 IS = 0 TPG = -1 ) 
**************************************************************** 
.MODEL DBD D ( 
+FC = 0.1 TT = 2.411e-08 T_MEASURED = 25 BV = 31 
+RS = 1.998e-02 N = 1.120e+00 IS = 3.532e-12 
+EG = 1.114e+00 XTI = 1.897e+00 TRS1 = 3.186e-04 
+CJO = 2.689e-11 VJ = 1.106e+00 M = 6.021e-01 ) 
.ENDS 
